1. Field of the Invention
The present invention relates to a method of manufacturing semiconductors, and more particularly, to a patterning method.
2. Description of Related Art
With development of semiconductor manufacturing technologies, critical dimensions (CDs) of features are minimized while integration of integrated circuits is continuously enhanced. In order to satisfy requirements for high density and great performance, it is necessary to precisely control the CDs of various features, profiles thereof, and uniformity thereof. In a complementary metal oxide semiconductor (CMOS) technology, a gate structure of a transistor is a key factor. Variations in the CDs and the profiles may give rise to speed differences, and reliability of devices is correspondingly affected. Accordingly, it is crucial to control a photolithography and etching process implemented for fabricating the gate structure.
In a typical manufacturing process of etching a polysilicon gate, different products may be produced in different recipes. That is to say, same types of products are fabricated in a certain recipe. The manufacturing process is usually carried out by performing a main etching step in a constant time, so as to etch a polysilicon layer to some degree. Thereafter, an etching endpoint detection step is implemented under different manufacturing conditions. Finally, an over etching step is performed under another manufacturing condition, so as to ensure that the polysilicon layer on a substrate is thoroughly etched. However, due to variations in manufacturing environment and in the manufacturing conditions, patterns formed by etching the polysilicon layer on within wafer or on without wafer are not completely the same and have undesired uniformity, which significantly reduces reliability of the devices.
U.S. patent publication No. 2007/0020777 discloses a method of controlling a formation of semiconductor devices. According to the disclosure of the '777 patent, a time required for performing an over etching step is determined and controlled based on both a correlation between a gate profile and a shallow trench isolation (STI) structure and a correlation between the gate profile and an over etching time, such that a gate formed through said method has a desired gate profile. However, referring to FIG. 1A, to achieve the desired gate profile, a longer time is usually required for performing the over etching step when a gate structure 102 formed by the method is etched. As such, a substrate 100 is severely damaged, resulting in the formation of a recess 104 in a great depth. What is more, production yield is significantly reduced due to an excessively low etching rate of the over etching step and a comparatively long period of time spent on the over etching step. On the other hand, referring to FIG. 1B, the recess may be formed in a relatively small depth when the time spent on the over etching step is reduced for minimizing the damages to the substrate 100. Nevertheless, a foot-shaped profile may be formed at a lower portion 106 of the gate structure 102, as indicated in FIG. 1B.